Since efforts to improve a copper etching method have proven unsuccessful, a copper dual damascene process, which inlays copper in an interconnect line, has been developed as an alternative. The copper dual damascene process has been verified as an excellent process in terms of process affinity and cost reduction; although it had been confronted with practical barriers in terms of manufacturing apparatus due to completely different structures and across-the-board changes.
FIGS. 1a through 1c are cross-sectional views illustrating a conventional process of forming a copper interconnect of dual damascene structure of a semiconductor device. Referring to FIG. 1a, a lower metal interconnect 11 is formed through an insulating layer on a substrate (not shown) having at least one structure. A capping layer 12 is deposited on the substrate including on the lower metal interconnect 11. The capping layer 12 is made of silicon nitride. A first insulating layer 13 is then deposited on the capping layer 12. The first insulating layer 13 is made of fluorinated silica glass (FSG) with a low dielectric constant. An etch-stop layer 14 is formed on the first insulating layer 13. The etch-stop layer 14 is made of silicon nitride. A second insulating layer 15 is then deposited on the etch-stop layer 14.
Referring to FIG. 1b, a via hole 16 is formed through the first insulating layer 13 by photolithographic and etching processes. The photoresist pattern for forming the via hole 16 is then removed. Next, by performing another photolithography process and another etching process using the etch-stop layer 14 as a mask, a trench 17 for an upper metal interconnect is formed through the second insulating layer 15.
Referring to FIG. 1c, some portion of the capping layer 12 is removed by using a dry etching process to form an opening 18 on the lower metal interconnect 11. The trench 17, the via hole 16, and the opening 18 are then filled with copper to complete a dual damascene interconnect connected to the lower metal interconnect 11.
In the above-described conventional process of forming a copper interconnect having a dual damascene structure, the via hole 16 is formed by sequentially dry-etching the second insulating layer 15, the etch-stop layer 14 and the first insulating layer 13. Therefore, a size difference between the upper part and the lower part of the etch-stop layer 14 is caused due to the etching selectivity between the etch-stop layer 14 and the second insulating layer 15. Such a size difference may cause void formation in a copper via line when the via hole 16 and the trench 17 are filled with copper by a copper plating process. Furthermore, although the etching rate to the etch-stop layer 14 has been made substantially equal to the etching rate to the second insulating layer 15 by improving the dry etching process, overhang may occur when a barrier metal layer of Ta/TaN and a copper seed layer are deposited in the trench 17 and the via hole 16 because the width of the trench 17 is larger than the width of the via hole 16. This overhang may cause void formation in a copper via line, thereby deteriorating the device characteristics.